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Aizyc SDIO (Secure Digital I/O) Device Controller IP is compact low power
and scalable IP core.
The SDIO device controller core supports SPI, 1-bit SD and 4-bits SD transfer modes.
It has fixed internal register map. The fixed area will contain information about the card and some mandatory and optional registers. The CIS and CSA will be implemented in internal memory of CPU subsystem. The SDIO registers (CCCR and FBR) can be programmed both by SD host through SD bus) and CPU (through OCP interface).
AHB Master & Slave interface in SDIO IP will allow easy integration in to SOC. Flexible architecture of the core will support wide range of applications – GPS , UWB, WiMAX etc.
The IP core is portable to an ASIC or a FPGA. It has been validated on Xilinx Spartan 3 platform.
Along with the IP core, we will provide complete test environment with constraint randomized test cases and our full support during integration.
- SDIO card specification version 2.00
- SD specification version 2.00
- Supports SPI, SD1 and SD4 modes
- 1-bit SD and 4-bit SD transfer modes
- Clock range
- 0-25MHz for full Speed card
- 0-50 MHz for high speed IO card
- SDIO features : Suspend/Resume,Interrupt, Read Wait
- Supports all SDIO commands including IO52 and IO53
- Programmable register through AHB interface
- System Bus Interface – AHB
- Optional Bus Interface - OCP, VCI, APB, AXI
- Multi-block read and write
- CRC7 and CRC16 checksum logic
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