VeriSilicon Holdings Co., Ltd. 
Short Desc. : SMIC18_PLL_05B---SMIC 0.18um 1.8v/3.3v PLL
Overview :
Designed for audio clock generation, this PLL integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other supportive circuits. The reference clock is either a crystal or an input clock from other sources and supports 8.192MHz/10MHz/12MHz/12.288MHz/13MHz/13.5MHz/19.2MHz/21.25MHz/24MHz/26MHz/38.85MHz as a reference.. The PLL supports 256*fs and 128*fs clock output, wherein fs is the audio system’s sample rate of 8kHz/11kHz/12kHz/16kHz/22kHz/24kHz/32kHz/44.1kHz/48kHz /96kHz.
Features : - Process: SMIC 0.18um Logic 1P6M 1.8V/3.3V CMOS process
- Supply voltage: 3.3v +/-10%; 1.8v+/-10%
- Output duty cycle: 45~55%
- Current: less than 0.5mA
- Operating junction temperature: -40~125°C
- More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/en/contactus.asp
Categories :
Portability :
Type : Hard
S2C: FPGA Base prototyping- Download white paper

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