Short Desc. : JPEG Decoder
Overview :
VISENGI's JPEG Decoder IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Decompressor / Decoder.
Features : - Baseline DCT decoder according to JPEG ITU-T T.81 | ISO/IEC 10918-1 standard
- Seamless Motion JPEG (MJPEG) decoding
- Dual pixel output to reach top speed (4 pixels decoded every 3 cycles)
- Maximum number of Huffman and Quantization tables allowed by specification (four each)
- Selectable maximum number of color components
- Unlimited chroma subsamplings, grayscale and multi-scan JPEGs
- Unlimited image size (specification up to 64K x64K)
- Allows RST (restart intervals) and DNL (for multi-scan images) markers
- Selectable YCbCr and/or RGB output
- Throughput: up to 4 pixels output every 3 clock cycles
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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