Short Desc. : JPEG Encoder
Overview :
This IP core has been developed to be a complete standards compliant JPEG Hardware Compressor / Encoder.
Features : - Baseline DCT compression according to JPEG ITU-T T.81 | ISO/IEC 10918-1 with JFIF 1.02 standard file header.
- On-the-fly selectable quality level/compression ratio from 1 to 100 before every compression (equivalent to SW solutions: IJG's JPEG lib., GIMP, IrfanView, etc.).
- Selectable chroma subsampling (4:4:4, 4:2:2 vert., 4:2:2 horiz., 4:2:0).
- Unlimited input image size (up to 64K x 64K as per JPEG spec.).
- Continuous data mode (input one image after another).
- Data input: 24 bits RGB pixels.
- Data output: 8 bits bus sequential output of the final JPEG image file's bytes.
- Optional modules: EXIF support, Motion JPEG (MJPEG) support, Restart marker support.
- Throughput: 2 compressed pixels every 3 clock cycles (up to 135 Mpix/s, or 405 Msamples/s, in a Virtex-5 FPGA).
Categories :
Portability :
Type : Hard
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

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