EnSilica Limited 
Short Desc. : Viterbi eSi-7590
Overview :
This IP core is available in either normal or high throughput configurations. The normal configuration instances a single fully parallel stage, equivalent to 32 ACS units, decoding a single message bit per clock cycle. The high throughput version instances 2 fully parallel stages, equivalent to 64 ACS units, and an interleaved traceback memory architecture. This decoder produces 2
message bits per clock cycle, twice that of conventional Viterbi decoders.
Features : - Constraint length 7.
- Generator polynomials g0 = 1338 g1 = 1718.
- Decoding 1 or 2 message bits per clock cycle.
- Block based traceback from best state.
- Optional trellis start state for packetised data.
- Optional trellis end state for packetised data.
- Low latency equal to 2.5x block length.
- Signed 6-bit soft decision (LLR) inputs for multilevel QAM decoding.
- De-puncturing support.
- Automatic normalization.
- Parameterisable soft core
Categories :
Portability :
Type : Soft
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