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 Innovative Integration 
Part Number : IP-DDC-2GSPS
Overview :
The IP-DDC-2GSPS core has 4 DC-RF frequency agile
digital down conversion channels. The core can process up
to 2GSPS input data. As a flexible front-end to receivers and
imaging devices, this core implements the frequency
translation for baseband signal recovery as FPGA firmware.
Features : - 4 individually tuned DDC channels
- 16 bit 2GSPS input
- Frequency agile bandpass filter
- Tuning resolution Fs/2^32
- SFDR 96 dB for 16 bits input
- Decimation range from 128 to 32768
- Programmable 48 tap frequency agile bandpass filter (16 bit coefficient)
- Programmable 20 tap FIR (18 bit coefficient)
- Programmable 80 tap FIR (18 bit coefficient)
- Up to 60 dB gain
- SFDR 96dB with 16 bit input
- Clock/sync bus for multi-module synchronization
- Test sine wave generator (SFDR 96dB)
- Overflow indicator
- DC remover
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



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