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 Innovative Integration 
Part Number : IP-DDC128
Overview :
The IP-DDC128 core has 128 output channels of digital
down-conversion (DDC). As a flexible front-end to receivers
and imaging devices, this core implements the frequency
translation for baseband signal recovery as FPGA firmware.
Features : - 128 individually tuned DDC channels
- 16 bit 200MHz input
- Tuning resolution Fs/2^32
- SFDR 96 dB for 16 bits input
- Decimation range from 512 to 8192
- FFT channelizer
- Programmable 20 tap FIR (18 bit coefficient)
- Programmable 80 tap FIR (18 bit coefficient)
- Up to 60 dB gain
- Clock/sync bus for multi-module synchronization
- Test sine wave generator (SFDR 100dB)
- Overflow indicator
- DC remover
- Power meter (-77dBm ~ 13dBm)
- Supports Xilinx Virtex5 FPGA
- Bit-true, cycle-true MATLAB model
Categories :
Portability :
Type : Soft
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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