||- Built-in DMA engine for autonomous data transfer.
- Internal data buffer to maximize data bandwidth.
- Optional ECC correction with BCH code for 4, 8, 12 or more error bits per 512 bytes.
- Stores ECC code in spare column area.
- Write-triggered read operation eliminates long wait states when open a new page,
- Enable NAND Flash to be used as BOOT ROM.
- Compatible with standard FTL software and Linux JFFS2 for wear leveling and bad block management.
- Designed for ASIC and FPGA implementation