VeriSilicon Holdings Co., Ltd. 
Short Desc. : G13LPDG_VDT_01---The present IP is a VCC Detector (VDT) circuit. It detects the voltage level of I/O (VIN).
Overview :
The present IP is a VCC Detector (VDT) circuit, which prevents the possibilities of causing Flash writing failure or internal operation failure by unstable supply voltage. It detects the voltage level of I/O (VIN). When the voltage is in the range of VTLL to VTLH, the output OUT_RD is generated as a high level. When the voltage is lower than VTLL or higher than VTLH, the output OUT_RD is generated as a low level.
This IP can’t stand-alone because it needs 0.5uA bias current and 1.0v reference voltage from external bandgap. The output may be in the wrong voltage level during the power-up phase before the bandgap becomes stable.
Features : - Process: GSMC 0.13um IBLP 4P5M e-flash Dual Gate Process(1.5v/HV)
- MOS devices being used: nch pch nchh_wo1 pchh
- Supply voltage: 1.5v±10%.
- Voltage detection range: VIN: 2.6v±0.1v ~ 5.65v±0.15v
- Typical operating current: 15uA @TT 25°C
- Power down leakage current: 20nA @TT 25°C
- Operating junction temperature: -40°C ~ +25°C ~ +125°C
- More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/en/contactus.asp
Categories :
Portability :
Type : Hard
S2C: FPGA Base prototyping- Download white paper

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