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 TurboConcept 
Short Desc. : TC1700: Turbo decoder Core for HSPA+, LTE and WiMAX
Overview :
The Core can be implemented in Base station or CPE receivers. It is optimized for ASIC and FPGA targets. The Core uses a unique architecture that reduces by more than 50 % the silicon area when compared to separate single-mode Cores, with no restrictions on the flexibility and features set. The Core is based on our robust and silicon-proven architecture that has been adopted by leading 4G system-on-chip manufacturers. The corresponding encoder Cores are also available with similar functional coverage.
Features : - Full coverage of 3GPP-HSPA+
- block sizes range : 40 to 5114 bits
- rate-matching
- Full coverage of 3GPP LTE specifications
- block sizes range : 40 to 6144 bits
- rate matching: support of depuncturing, sub-block deinterleaving
- CRC decoding
- Full coverage of IEEE802.16d/e WiMAX specifications
- maximum block size: 60 or 600 bytes (selectable)
- depuncturing, sub-block deinterleaving
- Block-by-block change of physical layer mode (HSPA+/LTE/WiMAX), block length, and number of iterations
- Throughput up to 500 Mbps decoded with 4 iterations (please contact us for device-specific figures)
- Dynamic stopping capability for reducing average number of iterations
- Latency reduction by bank swapping
- No external memory required
- Channel BER estimator
Categories :
Portability :
Type : Soft
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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