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 Tensilica 
Short Desc. : Diamond Standard 106Micro
Overview :
The Diamond Standard 106Micro CPU is Tensilica's smallest 32-bit RISC controller, designed for lowest area and lowest power. This cache-less controller is ideal for designers looking for a basic 32-bit controller, particularly for those migrating up from an 8- or 16-bit controller. It enables SOC architects to integrate an efficient CPU in their designs, with the added benefit of extremely quick time-to-market.
Features : - Tensilica's smallest, lowest power 32-bit RISC controller core
- Cache-less processor with memory protection unit
- 5-stage pipeline
- Dhryston MIPS: 1.22 DMIPS/MHz
- 24-/16-bit ISA with modeless switching
- Iterative 32x32 multiplier
- Separate instruction and data memory interfaces
- Integrated interrupt controller with 15 interrupts at 2 priority levels
- Integrated timer
- On-chip debugging hardware
- Embedded trace support
- Comprehensive software design environment
- AHB-lite and AXI bridges
Categories :
Portability :
Type : Soft
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