Short Desc. : Diamond Standard 212GP
Overview :
The Diamond Standard 212GP CPU is a high-performance, versatile, fully synthesizable 32-bit RISC CPU controller core. It is area and power efficient with a local memory architecture that provides outstanding flexibility and performance. Users can take advantage of Tensilica’s lockable cache and attach any size single-cycle instruction or data SRAM up to 128Kbytes
Features : - High performance with minimal die area, minimal power
- 5-stage pipeline
- Dhrystone 2.1: 1.38 DMIPS/MHz
- 32x32 multiplier and 32-bit integer divider
- 16-bit DSP instructions
- 8Kbyte, 2-way instruction and data caches
- 32-bit input/output GPIO ports for direct communication
- Integrated interrupt controller with 22 interrupts at 6 priority levels
- Three integrated timers
- Single-cycle XLMI interface
- On-chip debugging hardware
- Embedded trace support
- Comprehensive software design environment
- AHB-lite and AXI bridges
Categories :
Portability :
Type : Soft
CST: Webinars Begin on February 9

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy