Sarance Technologies Inc. 
Short Desc. : Interlaken Protocol
Overview :
Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10Gbps to 100Gbps
and beyond. Using the latest SERDES technology and a flexible protocol layer, Interlaken minimizes the pin and power
overhead of chip-to-chip interconnect and provides a scalable solution that can be used throughout an entire system. In
addition, Interlaken uses two levels of CRC checking and data scrambler to ensure data integrity and link robustness.
Features : - Compliant with the Interlaken Protocol Definition, Revision 1.1
- Support for up to 8.5 Gbps serial data rate
- Programmable BurstMax, BurstMin, BurstShort and MetaFrameSize parameters
- Data striping and de-striping across 1 to 20 lanes (limited by FPGA I/O resources)
- 64/67 encoding and decoding
- Automatic word and lane alignment
- Self-synchronizing data scrambler
- Configurable internal data bus width of 64, 128, 256 or 512bits
- CRC24 generation and checking for burst data integrity
- CRC32 generation and checking for lane data integrity
- Data scrambling and disparity tracking to minimize baseline wander and maintain DC balance
- Support for Synchronization, Scrambler State, Diagnostic, and Skip Word Block Types
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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