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Short Desc. :
Block Turbo Code decoder (BTC)
The TPC Encoder core is designed to operate in local multi-point distribution service (LMDS) and multi-channel
multi-point distribution service (MMDS) communication systems.
The core is especially useful for those communication links that require high data rates, low latency, high code rates,
high spectral efficiency, and a high degree of forward error correction capability.
Turbo Product Codes offer a higher performance alternative to Reed-Solomon or Reed-Solomon concatenated with Viterbi
error correction methods.
- Performs TPC decoding as defined in the IEEE 802.16 and 802.16a standards.
- Block sizes from 64 bits to 4 Kbits, 64 possible product codes.
- Support of external early termination + optional internal early termination at even/odd half iterations for higher throughputs.
- The following rates had achieved for FPGAs:
- Single-SISO option achieves a data rate of 9 Mbps with five iterations using (64,57)^2 code, average rate can achieve a 28 Mbps.
- Four-SISO option achieves a data rate of 36 Mbps with five iterations using (64,57)^2 code, average rate can achieve a 112 Mbps.
- Eight-SISO option achieves a data rate of 72 Mbps with five iterations using (64,57)^2 code, average rate can achieve a 225 Mbps.
- Sixteen-SISO option achieves a data rate of 144 Mbps with five iterations using (64,57)^2 code, average rate can achieve a 450 Mbps.
- Single-SISO option requires 721 FFs, 74,668 RAM bits (single port).
- Fully synchronous design using a single clock.
- Simple and efficient interface to control the decoder operation.
- Available for ASIC/FPGA designs as verilog source code or as netlist.
Forward Error Correction
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