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Short Desc. :
Convolutional Turbo Code decoder (CTC)
The nature of trellis paths is that once an error occurs it yields a burst of errors (till path converges again with original path).
The principle of Turbo Codes is to break sequences of errors into isolated errors that can be corrected in next iteration. The spreading of the error sequence is done with the interleaver. The interleaving function is extremely important, since poor interleaving functions can cause to error floor of the decoder.The base decoder is Max Log MAP with LLR scaling. This decoder gives only -0.1 dB performance compared with MAP/log MAP decoders, but ~40% smaller.
Decoder algorithm runs at 1 clock per 1 decoded bit. Termination of both RSCs is done as described in the 3gpp standard. Another termination method of terminating only the upper RSC while leaving the lower RSC open is available by demand. The advantage of this method is using only 3 tail bits instead of 6 while not having measurable degradation in performance.
- K=4 (8 states).
- Rate 1/3, other rates can be achieved with external puncturing.
- Up to 6.7 Mbit/s at full 8 iterations with Altera Stratix/Cyclone or Xilinx Virtex2. Up to 4.7 Mbit/s at full 8 iterations with Xilinx VirtexE, up to 105 Mbit/s with less iterations. (*)
- 2 early decoder termination mechanisms to support high throughputs (optional). User can halt the decoder at any time with the manual abort command.
- Compliant with 3GPP.
- Block length of 40-5114.
- All-synchronous design using a single clock, except for global asynchronous reset.
- Simple processor interface for easy programming of configuration registers.
- Available as verilog source code or as netlist.
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