||- Support all codes defined in the standard: 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6.
- Support all 19 codes lengths, from 576 to 2304 bits.
- Programmable number of iterations.
- Internal convergence test stops the decoder when data is fully recovered (0 errors).
- Decoded data rate exceeds 12-20 Mb/s (rate depended) with 10 iterations using 1 PU at 200-MHz clock frequency.
- Code synthesizable to ASIC and FPGA.