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 Xelic, Inc. 
Part Number : XCS12CM
Overview :
The Xelic SONET/SDH Concatenated Multi-Rate Framer Core (XCS12CM) aligns incoming SONET/SDH frames and provides transport overhead processing, path overhead processing and pointer processing for contiguous concatenated SONET/SDH payloads types. The XCS12CM contains independent Transport Processor and Concatenated Path Processor modules with a configuration option for STS-3/STM-1 or STS-12/STM4 SONET/SDH frame rates. Incoming/outgoing data is transferred using a clock valid scheme with an input clock rate up to 100Mb/s using an 8-bit data bus.
Features : - Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- The XCS12CM core is available under flexible single use licensing terms with netlist or source code deliverables.
- Implements clock valid scheme for variable data flow applications.
- Supports configurable STS-3/STM-1 and STS-12/STM-4 SONET/SDH frame rates.
- Compliant with ITU-T G.707 and Telcordia GR-253-CORE Specifications.
- Supports transport and path overhead blanking.
- Supports optional SONET/SDH frame scrambling for diagnostic purposes.
- Calculates and inserts B1/B2/B3 parity information with optional corruption capability.
- Provides capability to force MS AIS, path AIS, or LOS insertion.
- Provides ability to force pointer increment and decrement operations.
- Supports incoming frame alignment with OOF and LOF algorithm state transition signaling.
- Supports optional SONET/SDH frame descrambling for diagnostic purposes.
- Detects LOS, LOF, OOF, B1error, B2 error, B3 error, Path AIS, and MS AIS conditions.
- Calculates and compares extracted B1/B2/B3 parity for all incoming SONET/SDH frames.
- Detects LOP, pointer interpreter increments, decrements, pointer NDF, and pointer 3 in a row events
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



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