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Short Desc. : RXAUI IP Core
Overview :
The LogiCORE™ IP RXAUI core is a high-performance,low pin count 10-Gbps interface intended to allow physical separation between the data-link layer and physical layer devices in a 10-Gigabit Ethernet system.
Features : - Designed to Dune Networks RXAUI specification
- Uses two Virtex-6 FPGA GTX transceivers at 6.25
- Gbps line rate to achieve 10-Gbps data rate
- Implements DTE XGXS, PHY XGXS, and
- 10GBASE-X PCS in a single netlist
- Uses Virtex-6 FPGA Mixed-Mode Clock Managers
- Uses device-specific transceivers for the RXAUI
- interface
- IEEE 802.3-2005 clause 45 MDIO interface
- (optional)
- Available under the Xilinx End User License
- Agreement
Categories :
Portability :
Type : Soft
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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