Avalon Microelectronics 
Short Desc. : OIF Serial Framer Level 5 (SFI-5) IP Core
Overview :
This document details the SFI-5 interface macro from Avalon Microelectronics. The SFI-5 interface is a 17 lane interface with 16 data lanes and 1 parity lane, with each lane running at 2.5G – 3.125G. The clock and data is recovered from the individual data and parity lanes from the SERDES interface. The data is subsequently retimed to the system clock for framing and deskew.
Features : - OIF SFI-5 compliance
- Verilog RTL
- exceeds OIF skew standards: up to 16 bits of deskew
- Supports up to 56G data rates
- Each lane reports its current skew position
- Individual Lane Out of Alignment (OOA) alarms
- Per lane PRBS for integrity checking
- Support for Altera S2GX, Xilinx V5 devices
- Easy to interface, only datapath and clock needs to be connected to the system
- High Speed (256 bit - up to 200 MHz)
- Standard Data Rates supported:
- SONET OC-768
- SDH STM-256
Categories :
Portability :
Type : Soft
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