Rapid Bridge, LLC 
Short Desc. : XAUI SerDes
Overview :
10 Gigabit (X) Attachment Unit Interface (XAUI) PHY
Features : - "IEEE802.3ae Compliant
- 1.06-6.4 Gbps for CEI-6/XAUI applications
- Full , Half and Quarter Rate options
- Very low jitter generation
- Adaptive Receiver equalization for enhanced jitter tolerance
- Amplitude and pre/post-emphasis options
- Eye width mapping and on chip jitter test features
- Power saving modes
- Signal detection
- ± 100 ppm offset
- 8-, 10- , 16-, 20-bit parallel interface
- 8B10B Encode/Decode, Comma Detection and symbol alignment
- BIST circuitry with multiple pattern generation capabilities
- Multiple loopback test circuitries
- Multiple error status signals
- IEEE1194.1 and 1194.6 DC and AC JTAG support"
- The Rapid Bridge 10 Gigabit (X) Attachment Unit Interface (XAUI) is compliant with the IEEE802.3ae 10GbE specification. XAUI is the standard for connecting to an Ethernet MAC on a printed circuit board. This PHY consists of a hardened Physical Media Attach (PMA) layer that is programmed to meet different system link budgets and configuration requirements, and a soft Physical Coding Sublayer (PCS) that is intended to be programmed for different applications and form factors. Multiple 4-lane configurations are available in LiquidASIC offering. These may be further extended or modified to meet specific requirements in LiquidSoC offering. A wide range of transmit amplitudes and pre- and post- emphasis (de-emphasis), coupled with receiver equalization options, allow for optimum link budgeting of the overall system. PIPE interface is programmable to 8 or 16 bits. The Clock and Data Recovery (CDR) circuit allows for different levels of filtering and loop bandwidths to accommodate ppm offset. This PHY also supports Spread Spectrum Clock source. The 8B/10B encoder and decoders are provided as part of the PCS layer to allow for full programmability and function extension. A wide range of reference clock inputs are supported to meet different system requirements and clocking schemes. PCS layer also incorporates comma detection and word symbol alignment. The XAUI PHY incorporates high-level built-in test functions. It supports three different loopback modes: serial loopback, line-side loopback and parallel loopback. A centralized BIST consists of a pattern generator on the transmit side and a pattern verifier block on the receive side. Multiple patterns in support of different standards may be generated by the BIST block. The pattern verifier block aligns itself with the generated pattern and records number of mismatches in the captured data. This PHY also supports IDDQ testing and DC and AC JTAG in accordance to IEEE1149.1 and 1149.6. All receive and transmit on-die terminations are automatically calibrated to ensure proper return loss across the frequency spectrum. Architecture of XUAI results in low level of jitter generation that is well below the IEEE802.3ae requirements for bother deterministic and sinusoidal jitter components.
Categories :
Portability :
Type : Hard

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