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 Rapid Bridge, LLC 
Short Desc. : PCI-E GEN 1/2 SerDes
Overview :
Gen 1/2 2.5/5.0 Gbps PCI Express v1.0/v2.0 serial link PHY
Features : - "2.5Gbps/5.0Gbps
- PCI Express v1.1/v2.0 Compliant
- Amplitude and de-emphasis control
- Electrical Idle signaling and detection
- Receiver detection circuitry
- P0, P0S, P1, and P2 Power saving/modes
- Supports Mobile Graphics Low-Power Addendum
- Supports Wireless form factor extension
- Spread Spectrum Clocking
- ±600 ppm clocking offset
- Port Bifurcation factors of 1X, 4X, or 8X
- PIPE compliant interface
- 8B10B Encode/Decode, Comma Detection and symbol alignment
- PCI_Express compliant BIST circuitry patterns
- Multiple loopback test circuitries
- Multiple error status signals
- IEEE1194.1 and 1194.6 DC and AC JTAG support"
- Rapid Bridge's 2.5/5.0Gbps PCI Express v1.1/v2.0 serial link PHY is suitable for Root Complex and End Point applications. This PHY provides support for a number of PCI Express addendums and extensions including Mobile Graphics Low power and Wireless Form factor applications. This PHY is comprised of a hardened Physical Media Attach (PMA) layer that is programmed to meet different system link budgets and configuration requirements, and a soft Physical Coding Sublayer (PCS) that is intended to be programmed for different applications and form factors. Different lane configurations from 1 to 32 lanes are available in LiquidASIC offering. These may be further extended or modified to meet specific requirements in LiquidSoC offering. Wide range of transmit amplitude, pre and post emphasis (de-emphasis) coupled with receiver equalization options allow for optimum link budgeting of the overall system. PIPE interface is programmable to 8 or 16-bits. Clock and Data Recovery (CDR) circuit allows for different levels of filtering and loop bandwidths to accommodate ppm offset. This PHY also supports Spread Spectrum Clock sources. 8B/10B encoder and decoders are provided as part of the PCS layer to allow for full programmability and function extension. A wide range of reference clock inputs are supported to meet different system requirements and clocking schemes. The PCS layer also incorporates comma detection and word symbol alignment. Electrical idle detection and beacon signaling are supported by receivers and transmitters, allowing for PCI Express power saving modes (P0, P0S, P1 and P2). For Root Complex applications, port bifurcation is supported where multiple lanes are configured into individual links of 1 or more lanes each. PCI Express incorporates high level built-in test functions. It supports three different loop back modes: serial loop back, line-side loop back and parallel loop back. A centralized BIST consists of a pattern generator on the transmit side and a pattern verifier block on the receive side. Multiple patterns in support of different standards may be generated by the BIST block. Pattern verifier block aligns itself with the generated pattern and records number of mismatches in the captured data. This PHY also supports IDDQ testing and DC and AC JTAG in accordance to IEEE1149.1 and 1149.6.
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Portability :
Type : Hard
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