Rapid Bridge, LLC 
Short Desc. : DDR2 PHY
Overview :
JEDEC79-2A/B compliant highly integrated DDRII Physical Layer
Features : - "400-1066 Mbps
- Pre-configured bus in 32/64/72 bit widths
- 128Mb-4Gb addressable locations, single or dual ranks
- Impedance-calibrated 50/75/175Ω ODT
- Calibrated output impedance of 18Ω with ½ strength option
- ¾ latency on during write cycle
- Minimal read latency achieved via parameterized pipelining
- High clock rates with minimal routing constraints
- Optional pipe insertion at the controller interface for ease of timing
- Integrated master and slave DLL with supply regulation and resolution up to 10 ps.
- Programmable delayed address and command lines
- Fully programmable within Rapid Bridge LiquidASIC and LiquidSoC
- JEDEC79-2A/B compatible, Fully DFI-Compliant
- "
- Double Data Rate 2 (DDRII) is a high-bandwidth data transfer specification governed by JEDEC79-2A/B; it connects a Dynamic Random Access Memory (DRAM) chip or Dual Inline Memory Module (DIMM) to a processing chip in an electronic device or system. The Rapid Bridge DDRII LiquidPHY subsystem combines our patented IO architecture with PHY functions, test circuitry, and a third-party memory controller. This combination can be programmed and tested (via BIST) for a variety of applications. The physical implementation may be customized to meet different chip architectures and may wrap around single or multiple corners. The result is significantly reduced design and verification of memory subsystems. The Rapid Bridge approach yields a correct-by-construction solution that can be configured by the end user to a specific application for maximum silicon efficiency. The Rapid Bridge DDRII is fully DDR PHY Interface (DFI) compliant.
Categories :
Portability :
Type : Hard
S2C: FPGA Base prototyping- Download white paper

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