Rapid Bridge, LLC 
Short Desc. : DLL Master
Overview :
Low power regulated Master Closed loop master DLL intended for interface application
Features : - " 200-1400Mbps
- A: 200-700Mbps
- B: 350-850Mbps
- C: 750-1050Mbps
- D: 800-1400Mbps
- 7-bit, 128 stage delay elements
- Resolution of 8 to 16ps
- < 4mW power dissipation
- DLL lock function
- Regulated supply voltage for high supply noise rejection
- IDDQ, scan and bypass modes
- Metal programmable within Rapid Bridge platform"
- The Rapid Bridge Master and Slave Delay Lock Loop (DLL) family is intended for source-synchronous interface applications where eye-centering is required. This Master DLL determines a 7-bit code that corresponds to 90º phase offset (based on a reference clock). 7-bit code is transmitted to Slave DLLs that in turn convert the code to a respective delay equaling the 90º phase shift. A Slave DLL may be inserted in an open loop path and provided eye-centering. Master and Slave architecture is intended for DDR applications and is applicable to continuous or non-continuous strobe signaling. Both Master and Slave delay elements operate on regulated supply (also configured as master and slaves) for accuracy and incremental regulation, based on the interface width and requirements. Master and Slave DLLs are used in the composition of higher level LiquidPHYs such as DDRI/II/III, QDRI/II, GDDRIII/IV, RLDRAMI/II, PCI_X, RTBI etc.
Categories :
Portability :
Type : Hard
S2C: FPGA Base prototyping- Download white paper

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