Rapid Bridge, LLC 
Short Desc. : PLL Interpolator
Overview :
Low power 32 phase interpolator PLL intended for Clock Recovery Application
Features : - " 200-1800MHz output clock frequency
- A: 200-500MHz
- B: 400-800MHz
- C: 500-1000MHz
- D: 800-1400MHz
- E: 1000-1800MHz
- 2-bit pre-divider and 5-bit Multiplier
- < 10mW power dissipation
- Multiple copies of output clock @11.25º phase offset
- PLL slip function
- Less than 100µs
- Low Short term jitter
- 0.01/FCLKA ps
- Low Long term jitter
- 0.05/FCLKA ps
- High supply noise rejection
- IDDQ, scan and bypass modes
- Less than ± 2% duty cycle distortion across PVT
- Metal-programmable within Rapid Bridge platform
- Spread Spectrum Compliant"
- The Interpolator Phase Locked Loop (PLL) is designed to address accurate edge placement of an outgoing clock signal based on static phase alignment. A phase interpolator is used to provide any one of 32 phase alignments with a resolution of 360°/32, or 11.25°. The phase alignment may be complemented utilizing external logic algorithms to address clock/data recovery (CDR) or to capture data using training patterns. Different versions of the interpolator PLL (A-E) are provided to address a wide range of operating frequencies, from 200MHz to 1.8GHz, while maintaining adequate phase margins and loop dynamics. A 2(3)-bit N pre-divider and a 5(6)-bit M multiplier provide the end user with wide range of programmability for both input reference clock and output clocks. To simplify the overall system, 0°, 180°, 90° and 270° (absolute) phases of the output clocks are provided. This allows for capturing and processing data more effectively in architectures requiring both edge alignment and eye-centering. Duty cycle correction circuitry is provided to enable double-edge clocking schemes and to minimize overall system clock uncertainty and cycle-to-cycle jitter for DDR applications.
Categories :
Portability :
Type : Hard
S2C: FPGA Base prototyping- Download white paper

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