Short Desc. : SGC73 LDO - Low Noise High PSRR Series
Overview :
The SGC73 family of low-dropout (LDO), low-power linear regulator IP solutions for integration on SoC offers very high power supply rejection ratio (PSRR). The family uses advanced control techniques to achieve soft start-up, very low noise, excellent transient response, and excellent PSRR performance. The SGC73XXX is stable with a 1.0 µF ceramic output capacitor. It is specified from TJ = –40°C to +125 °C and is designed to achieve 3% overall accuracy (over Load/Line/Temp).
Features : - Low-Dropout Regulator (LDO) with enable
- Low IQ: 50 µA
- Available in multiple output versions:
- Fixed output with voltage from 0.8 V to 3.6 V in 50 mV steps using metal mask programming
- Programmable 16 ranges of output from 0.8 V to 3.6 V down to 50 mV steps with 4-bit DAC
- Available with six output current ranges: - from 25 mA to 300 mA
- Ultra-high PSRR: - 80 dB @ 20kHz; 70 dB @ 100kHz; 50 dB @ 1MHz
- Low Noise: 20 µV typical (20Hz to 20kHz)
- Large input range, from 1.8 V to 5.5 V
- Soft start and overcurrent protection
- Core area : 0.075 mm2
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
S2C: FPGA Base prototyping- Download white paper
TrueCircuits: IoTPLL

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