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Short Desc. : AMBA AHB Verification Component
Overview :
AMBA AHB VIP can be configured as Master, Slave and AHB bus and allows Module & System level verification. AMBA AHB VIP is a readymade highly configurable SystemVerilog Verification Component suitable for verification of AMBA AHB master and slave DUT. The AHB SV VIP provides all necessary building blocks to easily test master/slave DUT with the AHB protocol. The Verification Component can be easily configured and integrated with the verification environment.
Features : - Checking for AMBA AHB protocol through interface level assertion
- Master configuration to generate INCR packet to test slave master compatibility
- Added write protected area detection for verifying the slave with ROM
- Configurable slave memory size
- Random as well as user defined packet generation to hit particular scenarios
- Configuration of Lock or Unlock transfer
- Default master and default slave
- Wait state can be provided by user as per requirements
- Early Burst Termination
- System memory for slaves
- Dummy master
- Big endian/Little endian
- Protocol checkers/SV assertion
- Bus Monitor
- Functional Coverage
- DUT can be in Verilog or VHDL
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



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