|Short Desc. :
||OVM Module based SPI4.2 Verification Component
|OVM Module based VCs are reusableand can be used to establish ready-made verification environment. Each eVC is capable of acting as full verification environment or as a plug-in to an existing environment.
eInfochips' OVM Module based VCs are designed for verification of today's SoC designs. With their object-oriented architecture, eInfochips' eVCs are building blocks for establishing complex and comprehensive verification environment in very short time.
The SPI 4 interface is used for packet / cell transfer between physical layer and link layer devices for applications concerning aggregate bandwidth of OC-192 ATM , Packet over SONET/SDH and 10 Gb/s Ethernet. SPI 4 P2 OVM Module based VC represents the data link layer. It can be used to verify physical layer and data link layer devices that follow the SPI 4 P2 protocol. The OVM Module based VC consists of Packet Generator, Packet Analyzer, Functional Checker and Functional Coverage modules. It can work in both Verilog & VHDL environments and with HDL simulators that are supported by Specman.
||- Follows SPI4 Phase2 specifications from Optical Internetworking Forum (OIF)
- Supports 256 ports
- Source synchronous double edge clocking for data path
- Source synchronous clocking for FIFO status
- Supports on-the-fly pseudo-random packet generation
- Supports packet receiving and storage for analysis
- Generates Diagonally Interleaved Parity (DIP2 parity) for status path
- Injects data training sequences as per start-up parameters to maintain synchronization
- Injects FIFO training sequences on status path as per the start-up parameter
- Incorporates functional checker for both transmit and receive, data and status path Detects and reports errors such as:
- SOP position error
- Idle error
- Byte align error
- Training error
- Alpha violation error
- Synchronization error
- Built-in coverage analysis for bus transaction