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Short Desc. : AXI Slave Core
Overview :
The core provides efficient interface between custom slave and standard AXI bus. Parameterized design architecture makes core customization simple. A generic interface on slave side allows connecting user slave modules/devices easily.
AXI Slave core communicates with bus frequency on one side and
slave frequency on the other side.
Features : - Fully compliant to AMBA AXI protocol
- Supports AXI low power interface
- Support for exclusive access monitoring
- All types of AXI transfer bursts supported
- Generic third party slave interface for easy interface customization
- Supports isolation of custom interface from AXI with FIFO enabled for data and response
- Parameterized design architecture for FIFO
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

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