HDL Design House 
Short Desc. : HIP 3300
Overview :
The use of IP cores in ASIC, FGPA and system-on-chip
(SoC) designs has become a critical methodology as companies
struggle to address the need for rapid prototyping
and production. Reusable, drop-in components with predefined
functionality, IP cores speed the design cycle,
increase design quality and allow a greater degree of
innovation, enabling companies to reduce design costs
and create market differentiation.
Features : - Conforms to the RapidIO Interconnect
- Specification – Rev.1.3.
- The core supports one-lane high speed, (1x mode) or four lane (4x mode).
- The IP core includes the following features: Configurable modes of operation; supports
- 1x mode and 4x/1x mode
- 1.25 Gbaud/s, 2.5 Gbaud/s, 3.125 Gbaud/s
- 8B/10B Encoding and Decoding
- Error management extensions
- 34-bit addressing
- Clock and Data Recovery
- Lane Synchronization
- CRC Generation and Checking
- Packet/Control Symbol Assembly and Deassembly
- Supports all RapidIO packet sizes
- Synthesis: Synopsys/ Cadence FE
- Simulation: Modelsim, NC Verilog,
- Technology: 0.09u or better
Categories :
Portability :
Type : Soft

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy