||- Supports standard register set for the host controller
- Supports 32 bit AHB LITE synchronous Host interface working at SOC interface frequency.
- 1-bit/4-bit modes of SD/SDIO supported.
- One data Transmit FIFO with 32-bit write width and 256 depths.
- One data Receive FIFO with 32-bit read width and 256 depths.
- SDIO Interrupts, Suspend/Resume Operation and SDIO Read Wait Operation are supported.
- Buffers to store the response received.
- Command buffers to store command index and argument.
- Timeout monitoring for response and data operation.
- Card detect and removal monitoring using debouncing logic.
- Supports various clock frequencies such as 25MHz, 50MHz, 100MHz required for SD/ SDIO operations. Operating frequency configurable through registers.
- CRC generation / checking supported for both command and data transactions.
- Compliant with SD specification version 3.0