||- Highly configurable
- Flexible implementation using between 1 and 16 processors.
- Sizing of both data and instruction cache between 0k and 2Mbytes across each CPU.
- IP library with plug&play functionality allowing rapid and flexibility during SoC design.
- Optional high performance IEEE-754 Floating Point Unit.
- Optional SPARC Reference Memory Management Unit.
- High performance
- SPARC V8 architecture multiprocessor-capable instruction set architecture.
- 400 MHz on a 0.13 μm process, giving up to 6400 Dhrystone MIPS of performance.
- Built-in cache snooping for data coherency.
- Energy efficient
- Power down mode:
- Individual processor shutdown providing significant energy saving on dynamic power
- Clock gating:
- Each processor’s clock CPU can be individually gated-off in power down mode for
- further reduction of both dynamic and static power consumption.