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 Snowbush IP 
Short Desc. : TSMC 65LP PCI Express Gen1 PHY - SBPCIE2000T65LP - TSMC 65LP PCIe PHY
Overview :
The Snowbush PCIe PHY IP is a reliable, high-performance IP core designed to be easily integrated into PCIe devices found in consumer and server computing. The PCIe PHY IP is based on Snowbush's high-speed SERDES technology, which has an extensive production track record of volume shipments. To ease integration with PCIe controllers, the PCIe PHY IP utilizes the latest version of Intel's industry-standard PHY Interface for PCI Express (PIPE) defining the MAC/PCS functional partitioning and interface. The PCIe PHY is designed to exceed key electrical specifications and be extremely robust over PVT variations, while consuming low power and taking up minimal die area.
Features : - supports PCIe Gen1 (2.5Gb/s) and Gen2 (5.0Gb/s) supports single or multi-lane configurations

- PCS layer supports industry-standard PIPE interface

- supports all PCIe PIPE (P0, P0s, P1, and P2) power saving modes for ultra-low power operation

- programmable transmitter and receiver equalization

- transmit jitter and receiver jitter tolerance performance exceeding specifications

- leverages automatic digital calibration of key analog circuits to ensure reliability and to maximize yields

- wide range of test features including BIST, various internal loopback modes, and visibility into digital calibration
Categories :
Portability :
Type : Hard
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