|Short Desc. :
||Integrated Solution - PCI Express to DDR Controller/SBSUBPCIE2DDR
|This Snowbush SoC level IP provides an integrated end-to-end solution between PCI Express and DDR, consisting of three components:
* PCI Express Controller - Gen1, Gen2
* DDR 2 or DDR 3 Controller
* Bridge with SoC level features to connect both controllers listed above
||- Supports 1st Party DMA with ability to accept DMA Memory Write/Read commands from DDR Interface.
- Supports 1st Party DMA with ability to accept DMA Memory Write/Read commands from PCIe Master
- Multiple descriptors per DMA channels
- Handles out-of-order read-completions from PCIe targets
- Configurable DDR Databus - Master and Slave configurable to either 32bit or 64bit or 128 bit depending on the DDR DIMM Width.
- User selectable 5 variable windows from DDR to PCIe address translations
- User selectable 4 variable windows from PCIe to DDR address translations
- Up to 4 Base Address Registers (BARs) available in root mode address translation
- Interrupt Generation from local CPU to external CPU
- Interrupt generation from external to internal CPU