Magillem Design Services 
Short Desc. : Multi Channel DDR SDRAM Memory Controller
Overview :
The Memory controller is used to interface a DDR memory to an AHB, OCP or BVCI host system core, which doesn’t have an internal DDR controller. Several subsystems (N) can share the same controller. Each bus channel can be configured separately with asynchronous clocks management. This controller includes an AMBA APB port for configuration management.
Features : - Multi channels with AMBA AHB, BVCI or OCP Slave Interface
- AMBA APB Slave or PVCI Interface for DDR controller configuration
- Compliant AMBA AHB split capable
- Tools for Performance analysis
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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