Virage Logic Corporation 
Overview :
Virage Logic’s Application Specific IP (ASIP) Intelli Low Power DDR (LPDDR) Memory Controller is a flexible and advanced solution for ASIC, System-on-Chip (SoC) and FPGA designers requiring a lowpower and reduced area memory interface. The Intelli Low Power DDR Memory Controller provides a superior combination of low-power and high system bandwidth, while maintaining area optimization.
Features : - Complete JEDEC Standard Low Power DDR support
- Fully digital design for the entire controller
- Supports the entire range of Intelli Low Power DDR device speeds in 0.13um , 90nm and smaller processes
- Partial array self refresh saves power
- Advanced circuit design techniques further reduce on-chip power
- Clock gating
- Disabled unused state machines
- Memory chip power down and self refresh modes conserve memory power
- Lowest gate count- as small as 35K gates- reduces static power requirements
- Low latency for read to open page
- Support for out of order read request fulfillment
- Support for delayed writes
- Support for write combining
- Support for scheduler bypass for lowest possible latency
- Support for efficient partial burst transactions
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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