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 Xelic, Inc. 
Part Number : XCS768VM
Overview :
The Xelic SONET/SDH High Order VCAT/LCAS Mapper Core (XCS768VM) provides path overhead processing and pointer processing for any mix of SONET/SDH payloads
ranging from a granularity of STS-1 to STS-768c and performs high order (STS-1/VC-3-Xv or STS-3c/VC-4-Xc) virtual concatenation (VCAT) with link capacity adjustment scheme (LCAS) support enabling hitless dynamic bandwidth reprovisioning. The XCS768VM allows up to 256 individual channelized STS-1/VC-3’s or 256 STS-3c/VC-4 contiguous concatenated payloads to be
virtually concatenated into configurable groups (VCG’s) to provide flexible bandwidth allocation.
Features : - Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCSF core available under flexible single use licensing terms with netlist or source code deliverables.
- Supports Link Capacity Adjustment Scheme (LCAS) to provide for “right size” data transport optimization though High Order VCAT with granularity down to
- the STS-1 (VC-3) level.
- Provides hitless data add and remove capability.
- Provides processing for any mix of payloads ranging from a granularity of STS-1 to STS-768c including STS-1/VC-3-Xv or STS-3c/VC-4-Xc signals.
- Internal memory provides for 125us of differential delay compensation introduced between member paths in a VCG without external memory requirements.
- Provides an optional external memory interface for compensation of up to 256ms of differential delay.
- Inserts and interprets POH VCAT/LCAS H4 byte information.
- Provides corruption of H4 byte stage 1 (MFI1) and stage 2 (MFI2) multiframe information for diagnostic purposes.
- Provides transmit facility and terminal loopback options for diagnostic purposes.
- Implements 16-bit register interface for programming of internal registers.
- Compliant with ITU-T G.7042, G.7043, GR-253- CORE, and G.707 Specifications.
Categories :
Portability :
Type : Soft
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