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Short Desc. : PLLTS65GPFRAC - TSMC 65nm GP
Overview :
Operational mode where the feedback to the PLL is taken from the end of a clock tree, or some other circuit and the PLL operates to provide a known phase relationship between input reference clock and the output feedback clock.
Features : - Fully integrated multi-function CMOS PLL
- Constructed from proven building blocks to ensure first pass silicon success
- Wide functional range achievable:
- Input range 0.5MHz – 800MHz
- Output range 16MHz – 1.6GHz
- Delta Sigma fractional capability
- 24 bit fractional resolution
- 2nd order noise shaping
- Period Jitter less than 1.5ps RMS, 20ps p-p (6-sigma @1 GHz)
- Cycle-to-cycle jitter less than 2.2ps RMS, 30ps p-p(6 sigma @ 1GHz)
- Long Term Jitter less than 6ps RMS, 72ps p-p (6 sigma)
Categories :
Portability :
Type : Soft
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