Login

 Silicon Creations 
Short Desc. : PLLTS90GFRAC - TSMC 90nm G
Overview :
Operational mode where the feedback to the PLL is taken from the end of a clock tree, or some other circuit and the PLL operates to provide a known phase relationship between input reference clock and the output feedback clock. Deskew operation is usually used with small feedback divider ratios and only in integer mode.
Features : - Fully integrated multi-function CMOS PLL
- Constructed from proven building blocks to ensure first pass silicon success
- Wide functional range achievable:
- Input range 0.5MHz – 800MHz
- Output range 16MHz – 1.6GHz
- Delta Sigma fractional capability
- 24 bit fractional resolution
- 2nd order noise shaping
- Period Jitter less than 1.5ps RMS, 20ps p-p (6-sigma @1 GHz)
- Cycle-to-cycle jitter less than 2.2ps RMS, 30ps p-p (6 sigma @ 1GHz)
Categories :
Portability :
Type : Soft
CST Webinar Series
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy