Genesys Logic, Inc. 
Part Number : GL9711
Overview :
The GL9711 is a 1-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel's PHY Interface for the PCI Express Architecture rev. 1.0. It integrates one SerDes and the Physical Coding Sublayer (PCS) which performs 8b/10b encoding and decoding, elastic buffer and receiver detection, data serialization and deserialization. The SerDes in the GL9711 supports an effective serial interface speed (2.5 Gb/s) of data bandwidth, intended for use in ultrahigh-speed bi-directional data transmission system.
Features : - l Complies with PCI Express Base Specification rev. 1.0a
- l Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0
- l Integrates 2.5 gigabit per second (Gpbs) Serializer/Deserializer
- l Supports 8-bit or 10-bit parallel interface @250MHz
- l Supports 16-bit parallel interface @125MHz
- l Supports DDR configuration for 8-bit or 10-bit mode
- l Beacon transmission and reception
- l Receiver detection
- l Transmission and detection of electrical idle
- l Clock tolerance for 600 ppm in frequencies between bit rates at the two end of a Link
- l On-chip 8-bit/10-bit encoding/decoding and comma alignment
- l On-chip PLL provides clock synthesis
- l 1.8-V power supply for core
- l 2.5-V power supply for IO
- l Above 2.0 kV ESD protection
- l 0.18 mm process
- l Available in LFBGA-233 package
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

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