Part Number : DecFMA64
Overview :
DecFMA64 is the first Decimal Floating point Fused Multiply Add IP Core available in the market. It computes the Multiply-Add Operations ± (A×B) ±C of three inputs. DecFMA64 is fully compliant with IEEE 754r Standard. DecFMA64 inputs are encoded in the Decimal Interchange Format Encoding.
Features : - Full IEEE-754r compliance.
- Decimal64 (16 digits) format support.
- Decimal Interchange format encoding with Densely Packed Decimal (DPD) coding support
- 7 rounding modes support.
- Up 10 stages pipelining.
- The result is available every clock cycle
- Overflow, underflow, invalid, inexact operation flags.
- Tested with test cases compliant with IEEE-754r format.
- Full accuracy and precision support.
Categories :
Portability :
Type : Soft
TrueCircuits: IoTPLL

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