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 Multi Video Designs 
Short Desc. : DVB-S Modulator Core
Overview :
The MVD_DVB-S modulator includes all the processing functions between the MPEG_TS input and the DAC. It can be parameterized by using a very simple microprocessor like interface.
Real Time Controller & Null packet inserter,
Energy dispersal,
Reed-Solomon encoder,
Convolutional Interleaver,
FEC Convolution Encoder
Features : - For Virtex-5, Virtex-4 and Spartan-3/E/A FPGAs
- Flexible input and symbol rates
- Supported modes :
- Null Packet inserter Mode (User defined symbol rate)
- Genlock Mode (Symbol rate automatically defined by the input rate)
- Fully optimized single channel version
- Single clock (up to140 MHz+ for Spartan-3™,270 MHz+ for Virtex-4/5™
- Dynamically Programmable FEC
- 1/2, 2/3, 3/4, 5/6, 7/8
- Dynamically programmable DUC
- Deliverables :
- NGC or EDN files for specified FPGA family
- Back annotated VHDL for simulation
- Detailed datasheet and user’s guide
- Full behavioral VHDL design available (option)
Categories :
Portability :
Type : Soft
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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