Multi Video Designs 
Short Desc. : ASI Receiver Core
Overview :
The MVD ASI receiver core is a drop-in module that includes the following functions :
Clock/Data recovery,
Serial/parallel Conversion,
Sync Byte (FC Comma Detection),
8B/10B decoding,
Auto adaptation to 188/204 bytes packet Input,
Baud rate measurement,
Optional frame buffer,
188 bytes MPEG_ASI output,
Features : - Multi mode ASI receiver
- European standard EN50083-9 Annex B
- Drop-in module for Virtex-5™, Virtex-4™ and Spartan™-3/E/A FPGAs
- Supports 188 or 204 bytes packet input
- Supports 3 ASI interfaces Input :
- HOTLINK (Parallel Input)
- LVDS (separate Clock and Data Input)
- Combined (clock recovery from Data)
- Supports Data Packet or Data Burst format
- Single channel – support for multi channel
- Full synthetizable RTL VHDL design (not delivered) for easy customization
- Netlist version available for ISE 9.2 and later versions
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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