Login

 TurboConcept 
Short Desc. : 3GPP-LTE (TC7000-LTE)
Overview :
TC7000-LTE is a convolutional turbo code (CTC) decoder optimized for 3GPP/LTE specifications. It offers several algorithm options to meet various trade-offs between error correction performance versus Core complexity. The decoder architecture is high-throughput oriented for all block sizes.
Features : - Compliant with 3GPP-LTE
- Block size covered from 40 to 6144 payload bits, switchable on the fly
- Native code rate 1/3. Other code rates supported through rate matching (optional)
- Near floating point error correction performance
- High throughput Max-Log-MAP algorithm
- Efficient and flexible Log-MAP algorithm
- Multi-processor architecture, several throughput levels selectable before synthesis - from 25 to 150 Mbps decoded
- Efficient iteration stopping feature for reducing average number of iterations without performance degradation
- On-the-fly change of block length, number of iterations and selection of the Log-MAP algorithm
- Low latency
- Single FPGA Core (no external memory required), available on all popular Xilinx, Altera and Lattice devices
- ASIC Core : Verilog or VHDL RTL Core delivery
Categories :
Portability :
Type : Soft
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy