Embedded, IP & SoC News
Submit New Event
What Would Joe Do?
Submit New Tutorial
Submit New Video
Submit New YouTube Video
Submit New Download
EDA Media Kit
Banner Ad Specifications
eMail Blast Specifications
Digital Blocks, Inc.
Short Desc. :
APB Bus I2C Controller
The Digital Blocks DB-I2C-APB Controller IP Core interfaces a microprocessor via the AMBA 2.0 APB Bus to an I2C Bus. The I2C is a two-wire bidirectional interface, and the DB-I2C-APB can Master or Slave the interface in either Transmit or Receive modes. Figure 1 depicts the system view of the DB-I2C-APB Controller IP Core embedded within an integrated circuit device.
- Three versions available:
- Master-Slave combined
- Master only
- Slave only
- Master – Slave Modes:
- Master – Transmitter; Master – Receiver
- Slave – Transmitter; Slave – Receiver
- Supports Multi-master, Arbitration and Clock Synchronization
- Single 8-bit data buffer register or optional parameterized FIFO for higher performance
- Supports two I2C bus speeds:
- Standard mode (100 Kb/s)
- Fast mode (400 Kb/s)
- 7- or 10-bit addressing
- Digital filter for the received SDA and SCL lines
- 8 sources of internal interrupts with masking control
- Compliance with APB and I2C specifications:
- AMBA Specification (Rev 2.0), APB Bus
- Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000
- Fully-synchronous, synthesizable Verilog or VHDL RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states.
© 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 —
, or visit our other sites: