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 4DSP 
Short Desc. : JPEG compression core
Overview :
4DSP's JPEG compression algorithm for FPGA is based on the ISO/IEC 10918-1 standard. This intellectual property core can be implemented on the Xilinx Spartan 3, Virtex-II, and Virtex-4 FPGA families. Data is fed to the FPGA through a user selected interface and is compressed into a JPEG JFIF format.
Features : - Up to 500 frames/s
- Up to 2048 x 2048 images
- Up to 16-bit pixel resolution
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



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