Xelic, Inc. 
Part Number : XCO3FECD
Overview :
The Xelic OTN 40Gb/s FEC Decoder (XCO3FECD) core detects and corrects incoming errors using interleaved Reed Solomon (255,239) codes for Optical Transport Network applications. Interleaving is performed as outlined in specification G.709 with FEC codewords containing 255 byte symbols made up of 239 byte data symbols and 16 byte check symbols. The XCO3FECD can be parameterized to support 128 or 256 bit data widths.
Features : - Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- The XCO3FECD core is available under flexible single use licensing terms with netlist or source code deliverables.
- Implements flexible data bus architecture.
- Provides for normal and bypass modes of operation.
- Complies with ITU-T G.709 and ITU-T G.798 specifications.
- Corrects up to sixteen errors per codeword or 512 erroneous bytes per frame.
- Supports normal, sleep, and bypass modes of operation.
- Provides performance counters for the accumulation of FEC correctable symbols, correctable 0’s, correctable 1’s, and uncorrectable codewords.
- Supports configurable FEC bit error rate detection of 10-3 or 10-4.
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

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