Login

 VeriSilicon Holdings Co., Ltd. 
Short Desc. : GSMC18_ICG_01---GSMC 0.18um 1.8V/3.3V Clockgating Cell Library
Overview :
VeriSilicon GSMC 0.18um 1.8V/3.3V Clockgating Cell (01) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic 1P6M Salicide 1.8/3.3V process. This library supports both latch posedge and latch negedge type clock gating cell with multiple drive strengths and with/without postcontrol test function. While satisfying the performance and power requirements, it was optimized for area efficiency.
Features : - GSMC 0.18um Logic 1P6M Salicide 1.8V/3.3V process
- Supports posedge and negedge type clock gating cells
- Supports post-control test function
- Supports multiple drive strengths
- Suitable for four, five and six layers of metal
Categories :
Portability :
Type : Hard
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy