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VeriSilicon Holdings Co., Ltd.
Short Desc. :
GSMC25_SSTL2IO_01--GSMC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library
VeriSilicon GSMC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.25um Logic 1P7M Salicide 2.5/3.3V process. This library is fully compliant with the EIA/JEDEC standard, JESD8-9B Stub Series Terminated Logic for 2.5V (SSTL2) updated in Oct 2002. The SSTL2 provides MOS push-pull interface designs and is especially optimized for major memory applications. It is intended to improve operation in situations where busses must be isolated from relatively large stubs. Comparing to the LVTTL solution, SSTL2 has the advantages of lower voltage swing, lower power dissipation and higher immunity to generated noise thanks to the differential receiver. There are two classes of output specifications for SSTL2, class I and class II, which are distinguished by drive requirements and applications. Class I is basically applied in point-to-point configurations, such as network applications, and Class II is mostly applied in 266MHz DDR SDRAM signaling.
- GSMC 0.25um Logic 1P5M Salicide 2.5V/3.3V process
- 2.5V core and 2.5V external interface
- Meet SSTL2 DC input levels and SSTL2 AC output levels
- Cell count: 21 cells, which are 8 pad bodies, 2 power cut cells, 1 corner cell, 8 fillers, 2 pad heads
- Suitable for physical designs with four or five metal layers
- Easy interface with VeriSilicon GSMC 0.25um process standard I/O libraries
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