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 CorePool 
Short Desc. : FHG_DRM Base Band IP
Overview :
The CorePool component FHG_DRM offers a “pure-hardware” solution for Digital Radio Mondiale (DRM) base band decoding. The FHG_DRM IP is based on an proprietary signal processing architecture. This enabled a scalable implementation with a small footprint and minimal dependency on third party IP or specific silicon vendors or manufacturing technologies.
Features : - Implements the complete DRM base band processing, including signal acquisition and tracking, signal conditioning, viterbi and multi-level decoding.
- Interfaces to standard (analog) tuner frond ends and outputs digital bit stream (DRM service multiplex, MDI) to service/audio decoder.
- Fully synthesize-able, independent of any specific semiconductor manufacturer or process.
- Free of third-party intellectual property cores (e.g. CPU cores), no hardware related third-party IPR licensing issues or royalties.
- Minimal size (compared to DSP based base band solutions)
- flexible, arbitrary data bit-widths (minimized logic)
- enables clock/power vs. chip area trade-offs
- inherent parallelism, scales easily (e.g. for 2-arm diversity receiver)
- Available in different configurations and with different interface options, including interface option for I2C or for industry standard AMBA bus.
- Technology independent (FPGA and ASIC)
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



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