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 Xilinx 
Short Desc. : PLB PCI Bridge
Overview :
The PLB IPIF/ V3 PCI Core Bridge design bridges the PLB IPIF (On-Chip Peripheral Bus Intellectual Property Interface) and the PCI64 Interface v3.0 core providing full bridge functionality between the Xilinx 32-bit PLB and a 32-bit V2.2 compliant PCI (Peripheral Component Interconnect) bus. Only 33 MHz, 32-bit PCI buses are supported at this time. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit. The PLB to PCI 32/33 Bridge is offered as an evaluation core in the EDK. To generate a full PLB to PCI license, the PCI-32 LogiCORE must be purchased.
Features : - One of the infrastructure cores supported by the Embedded Development Kit (EDK)
- 33 MHz, 32-bit PCI buses
- Utilizes the SRAM interface of the PLB IPIF for PCI data transfers
- PLB and PCI clocks are required to be a global buffer
Categories :
Portability :
Type : Soft
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